1. Field of the Invention
The present invention relates to a semiconductor memory device having a memory cell portion and a peripheral circuit portion.
2. Description of the Prior Art
FIG. 1 shows a chip of a DRAM. Memory cell portions 11 indicated by the hatched portions in FIG. 1 and a peripheral circuit portion 12 arranged around the memory cell portions 11 are formed on the chip. An address decoder, a sense amplifier, and the like are formed in a region 13 of the peripheral circuit portion 12.
FIG. 2 shows an interface region 14 between the memory cell portion 11 and the peripheral circuit portion 12 in a conventional stacked capacitor DRAM. As shown in FIG. 2, an SiO.sub.2 film 16 serving as a field oxide film is formed in an element isolation region including the interface region 14 on an Si substrate 15 of the chip, and a memory cell is constituted by a MOS transistor 17 and a capacitor 18 in the memory cell portion 11.
The MOS transistor 17 comprises a gate electrode, e.g., a word line constituted by a polycide film 21, source/drain regions constituted by diffusion layers 22 and 23, and a gate oxide film constituted by an SiO.sub.2 film 24. The polycide film 21 and the like are covered with an interlayer insulator constituted by an SiO.sub.2 film 25 and the like, and a contact hole 26 reaching the diffusion layer 22 is formed in the SiO.sub.2 film 25.
The capacitor 18 comprises a storage node constituted by a polysilicon film 31 contacting the diffusion layer 22 through the contact hole 26, a capacitor insulating film constituted by an ONO film 32 or the like, and a plate electrode constituted by a polysilicon film 33. The polysilicon film 33 and the like are sequentially covered with an SiN film 34 having a thickness of several hundred .ANG. and an interlayer insulator constituted by an SiO.sub.2 -based film 35 such as an SiO.sub.2 film, a PSG film or the like.
A contact hole 36 reaching the polysilicon film 33 is formed in the SiO.sub.2 -based film 35 and the like, and a wiring constituted by a polycide film 37 is in contact with the polysilicon film 33 through the contact hole 36. The polycide film 37 and the like are covered with an interlayer insulator constituted by a BPSG film 41 or the like, and a contact hole 42 reaching the polycide film 37 is formed in the BPSG film 41.
A bit line constituted by a polycide film (not shown) is in contact with the diffusion layer 23. In the peripheral circuit portion 12, a contact hole 44 reaching a diffusion layer 43 is formed in the BPSG film 41 and the like.
Since the polycide films serving as the bit line or the like are generally of an n type, they can be brought into contact with only an n-type diffusion layer. For this reason, all the diffusion layers of the memory cell portion 11 including the diffusion layer 23 contacting the bit line are of an n type. However, since the peripheral circuit portion I2 also has a p-type diffusion layer, an A1 wiring (not shown) must be formed.
This Al wiring is used as a shunt of the bit line, the word line, or the like in the memory cell portion 11, and it is in contact with the polycide film 37 or the like through the contact hole 42 or the like. Therefore, the Al wiring is not in contact with the diffusion layer 23 and the like in the memory cell portion 11. In contrast to this, the Al wiring is in contact with the diffusion layer 43 or the like through the contact hole 44 or the like in the peripheral circuit portion 12.
However, the Al wiring has poorer step coverage than that of a wiring constituted by a polysilicon film or the like. For this reason, in the peripheral circuit portion 12 wherein the Al wiring is set in contact with the diffusion layer 43 or the like, as shown in FIG. 2, an unnecessary SiO.sub.2 -based film 35 is selectively removed by etching to cause the contact hole 44 or the like to be shallow. At this time, the SiN film 34 is used as a stopper.
When an interface state is present in a region 45 due to a dangling bond on the interface between the SiO.sub.2 film 24 and the Si substrate 15 in the region 45, the gate swing of the MOS transistor 17 is not steep so that a threshold voltage is increased. As a result, a write level of the capacitor 18 becomes low to decrease the storage charge amount of the capacitor 18, thereby degrading the data retention characteristics of the memory cell.
When an interface state is present in a region 46 due to a dangling bond on the interface between the SiO.sub.2 film 16 and the Si substrate 15 in the region 46, the interface state serves as a generation/recombination center. Although a p-n junction is formed between the Si substrate 15 and the diffusion layer 22, a current leaks from the diffusion layer 22 to the Si substrate 15 through the interface state. Therefore, due to this phenomenon, the data retention characteristics of the memory cell are degraded.
For this reason, hydrogen annealing is performed to terminate the dangling bonds on the Si interfaces in the regions 45 and 46 by hydrogen and eliminate the interface states in the regions 45 and 46.
When annealing at a temperature of about 500.degree. C. or more is performed after this hydrogen annealing is performed, bonds between Si and hydrogen are cut again. For this reason, the effect of the hydrogen annealing is decreased. Therefore, the hydrogen annealing is preferably performed after the annealing at the temperature of about 500.degree. C. or more is finished and the contact holes 42 and 44 for Al wiring are formed as shown in FIG. 2, i.e., immediately before the Al wiring is formed. Note that sintering performed after the Al wiring is formed is performed without any problems because the sintering is performed at a temperature of about 400.degree. to 450.degree. C.
However, as is apparent from FIG. 2, the SiN film 34 is formed on the entire surface of the resultant structure in advance immediately before the Al wiring is formed. Since this SiN film 34 has a very high density, it does not allow permeation of even hydrogen. For this reason, even when the hydrogen annealing is performed, hydrogen cannot be supplied to the Si interfaces in the regions 45 and 46.
A conventional DRAM has a large number of contact holes for causing the Al wiring to contact the diffusion layer of an Si substrate, and the contact holes extend through an SiN film. For this reason, hydrogen can be diffused through the contact holes set in an open state.
However, in a recent DRAM, unlike the above conventional DRAM, since the Al wiring is not in contact with the diffusion layer 23 or the like in the memory cell portion to obtain a structure having a high integration level, the contact hole 42 or the like used for the Al wiring does not extend through the SiN film 34. For this reason, an interface state cannot be eliminated by the hydrogen annealing. As a result, the data retention characteristics of the memory cell are degraded in the prior art shown in FIG. 2.